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mosel vitelic 1 v43648y04v(c)tg-75 3.3 volt 8m x 64 high performance pc133 unbuffered sodimm preliminary v43648y04v(c)tg-75 rev. 1.3 october 2000 features n jedec-standard 144 pin, small-outline, dual in line memory module (sodimm) n serial presence detect with e 2 prom n fully synchronous, all signals registered on positive edge of system clock n single +3.3v ( 0.3v) power supply n all device pins are lvttl compatible n 4096 refresh cycles every 64 ms n self-refresh mode n internal pipelined operation; column address can be changed every system clock n programmable burst lengths: 1, 2, 4, 8 or full page n auto precharge and precharge all banks by a10 n data mask function by dqm n mode register set programming n programmable (cas latency: 3 clocks) description the v43648y04v(c)tg-75 memory module is organized 8,388,608 x 64 bits in a 144 pin sodimm. the 8m x 64 memory module uses 8 mosel-vitelic 4m x 16 sdram. the x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. part number speed grade configuration v43648y04v(c)tg-75 -75 (133 mhz) 8m x 64 1 pin 2 on backside pin 144 on backside 59 61 143 4m x 16 4m x 16 4m x 16 4m x 16
2 v43648y04v(c)tg-75 re v . 1.3 october 2000 mosel vitelic v43648y04v(c)tg-75 pin configurations (front side/back side) note: 1. ras , cas , we cas x, cs x are active low signals. pin front pin front pin front pin back pin back pin back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vss vss dq0 dq32 dq1 dq33 dq2 dq34 dq3 dq35 vdd vdd dq4 dq36 dq5 dq37 dq6 dq38 dq7 dq39 vss vss dqmb0 dqmb4 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 dqmb1 dqmb5 vdd vdd a0 a3 a1 a4 a2 a5 vss vss dq8 dq40 dq9 dq41 dq10 dq42 dq11 dq43 vdd vdd dq12 dq44 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 dq13 dq45 dq14 dq46 dq15 dq47 vss vss nc nc nc nc clk0 cke0 vdd vdd ras cas we cke1 cs0 nc cs1 nc 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 nc clk1 vss vss nc nc nc nc vdd vdd dq16 dq48 dq17 dq49 dq18 dq50 dq19 dq51 vss vss dq20 dq52 dq21 dq53 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 dq22 dq54 dq23 dq55 vdd vdd a6 a7 a8 ba0 vss vss a9 ba1 a10 a11 vdd vdd dqmb2 dqmb6 dqmb3 dqmb7 vss vss 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 dq24 dq56 dq25 dq57 dq26 dq58 dq27 dq59 vdd vdd dq28 dq60 dq29 dq61 dq30 dq62 dq31 dq63 vss vss sda scl vdd vdd pin names a0Ca11, ba0, ba1 address, bank select dq0Cdq63 data inputs/outputs ras row address strobes cas column address strobes we write enable cs 0 , cs 1 chip select dqmb0Cdqmb7 output enable cke0, cke1 clock enable clk0Cclk1 clock sda serial input/output scl serial clock vdd power supply vss ground nc no connect (open)
mosel vitelic v43648y04v(c)tg-75 3 v43648y04v(c)tg-75 re v . 1.3 october 2000 part number information block diagram sdram 3.3v v43648y04v(c)tg-75-02 4 mosel-vitelic manufactured v 144 pin unbuffered sodimm x16 component y refresh rate 4k 0 3 depth 8 4 banks 4 width 64 lvttl v tsop gold 75 (133 mhz) pc133 g 75 t component revision level blank = rev b c = rev c c cs0 we v43648y04v(c)tg-75 -03 u0 u7 a0 a11, ba0, ba1 v dd u0 u3 cke0 u4 u7 ckei u0 u7 u0, u1 clk0 v ss u2, u3 10 scl sda 10 u4, u5 clki u6, u7 10 10 spd a0 a1 a2 dqmb4 dqmb5 dq32 39 dq40 47 udqm u2 ldqm dqmb0 dqmb1 dq0 7 dq8 15 udqm u0 ldqm dqmb6 dqmb7 dq43 54 dq55 63 udqm u3 ldqm dqmb2 dqmb3 dq16 23 dq24 31 udqm u1 ldqm cs we cs we cs we cs we cs1 we dqmb4 dqmb5 dq32 39 dq40 47 udqm u6 ldqm dqmb0 dqmb1 dq0 7 dq8 15 udqm u4 ldqm dqmb6 dqmb7 dq43 54 dq55 63 udqm u7 ldqm dqmb2 dqmb3 dq16 23 dq24 31 udqm u5 ldqm cs we cs we cs we cs we
4 v43648y04v(c)tg-75 re v . 1.3 october 2000 mosel vitelic v43648y04v(c)tg-75 serial presence detect information a serial presence detect storage device - e 2 prom - is assembled onto the module. informa- tion about the module configuration, speed, etc. is written into the e 2 prom device during module pro- duction using a serial presence detect protocol (i 2 c synchronous 2-wire bus) spd-table for 75 modules: byte number function described spd entry value hex value 8mx64 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type sdram 04 3 number of row addresses (without bs bits) 12 0c 4 number of column addresses (for x16 sdram) 8 08 5 number of dimm banks 2 02 6 module data width 64 40 7 module data width (continued) 0 00 8 module interface levels lvttl 01 9 sdram cycle time at cl=3 7.5 ns 75 10 sdram access time from clock at cl=3 5.4 ns 54 11 dimm config (error det/corr.) none 00 12 refresh rate/type self-refresh, 15.6 m s 80 13 sdram width, primary x16 10 14 error checking sdram data width n/a / x8 00 15 minimum clock delay from back to back random column address t ccd = 1 clk 01 16 burst length supported 1, 2, 4, 8 & full page 8f 17 number of sdram banks 4 04 18 supported cas latencies cl = 3 04 19 cs latencies cs latency = 0 01 20 we latencies wl = 0 01 21 sdram dimm module attributes non buffered/non reg. 00 22 sdram device attributes: general vcc tol 10% 0e 23 minimum clock cycle time at cas latency = 2 not supported 00 24 maximum data access time from clock for cl = 2 not supported 00 25 minimum clock cycle time at cl = 1 not supported 00 26 maximum data access time from clock at cl = 1 not supported 00 27 minimum row precharge time 20 ns 14 28 minimum row active to row active delay t rrd 15 ns 0f 29 minimum ras to cas delay t rcd 20 ns 14 30 minimum ras pulse width t ras 45 ns 2d
mosel vitelic v43648y04v(c)tg-75 5 v43648y04v(c)tg-75 re v . 1.3 october 2000 dc characteristics t a = 0 c to 70 c; v ss = 0 v; v dd , v ddq = 3.3v 0.3v 31 module bank density (per bank) 32 mbyte 08 32 sdram input setup time 1.5 ns 15 33 sdram input hold time 0.8 ns 08 34 sdram data input setup time 1.5 ns 15 35 sdram data input hold time 0.8 ns 08 62-61 superset information (may be used in future) 00 62 spd revision revision 2 02 63 checksum for bytes 0 - 62 8c 64 manufacturers jedec id code mosel vitelic 40 65-71 manufacturers jedec id code (cont.) 00 72 manufacturing location 1 = us, 2 = taiwan 73-90 module part number (ascii) v43648y04v(c)tg-75 91-92 pcb identification code current pcb revision 93 assembly manufacturing date (year) binary coded year (bcd) 94 assembly manufacturing date (week) binary coded week (bcd) 95-98 assembly serial number byte 95 = lsb, byte 98 = msb 99-125 reserved 00 126 intel specification for frequency 64 127 reserved 00 128+ unused storage location 00 symbol parameter limit values unit min. max. v ih input high voltage 2.0 v cc +0.3 v v il input low voltage C0.5 0.8 v v oh output high voltage (i out = C2.0 ma) 2.4 v v ol output low voltage (i out = 2.0 ma) 0.4 v i i(l) input leakage current, any input (0 v < v in < 3.6 v, all other inputs = 0v) C10 10 m a i o(l) output leakage current (dq is disabled, 0v < v out < v cc ) C10 10 m a spd-table for 75 modules: (continued) byte number function described spd entry value hex value 8mx64
6 v43648y04v(c)tg-75 re v . 1.3 october 2000 mosel vitelic v43648y04v(c)tg-75 capacitance t a = 0 c to 70 c; v dd = 3.3v 0.3v, f = 1 mhz operating currents t a = 0 c to 70 c, v cc = 3.3v 0.3v (recommended operating conditions otherwise noted ) notes: 1. these parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t ck and t rc . input signals are changed one time during t ck . 2. these parameter depend on output loading. specified values are obtained with output open. symbol parameter limit values unit max. 8m x 64 c i1 input capacitance (a0 to a11, ras , cas , we ) 10 pf c i2 input capacitance ( cs0 - cs3 ) 10 pf c icl input capacitance (clk0-clk3) 30 pf c i3 input capacitance (cke0, cke1) 10 pf c i4 input capacitance (dqm0-dqm7) 10 pf c io input/output capacitance (i/o1-i/064) 10 pf c sc input capacitance (scl, sa0-2) 8 pf c sd input/output capacitance (sa0-sa2) 10 pf symbol parameter & test condition max. unit note -75 icc1 o perating c urrent t rc = t rcmin. , t rc = t ckmin . active-precharge command cycling, without burst operation 1 bank operation 600 ma 7 icc2p precharge s tandby c urrent in power down mode cs =v ih , cke v il(max) t ck = min. 16 ma 7 icc2ps t ck = infinity 8 ma 7 icc2n precharge s tandby c urrent in non-power down mode cs =v ih , cke 3 v il(max) t ck = min. 160 ma icc2ns t ck = infinity 20 ma icc3 n o o perating c urrent t ck = min, cs = v ih(min) bank ; active state ( 4 banks) cke 3 v ih(min.) 200 ma icc3p cke 3 v il(max.) (power down mode) 64 ma icc4 b urst o perating c urrent t ck = min read/write command cycling 600 ma 7,8 icc5 a uto r efresh c urrent t ck = min auto refresh command cycling 1120 ma 7 icc6 s elf r efresh c urrent self refresh mode, cke=0.2v 8 ma l-version 4 ma
mosel vitelic v43648y04v(c)tg-75 7 v43648y04v(c)tg-75 re v . 1.3 october 2000 ac characteristics t a = 0 to 70 c; v ss = 0v; v cc = 3.3v 0.3v, t t = 1 ns # symbol parameter limit values unit note -75 min. max. clock and clock enable 1 t ck clock cycle time cas latency = 3 cas latency = 2 7.5 10 C C s ns ns 2 t ck clock frequency cas latency = 3 cas latency = 2 C C 133 100 mhz mhz 3 t ac access time from clock cas latency = 3 cas latency = 2 C _ 5.4 6 ns ns 2, 4 4 t ch clock high pulse width 2.5 C ns 5 t cl clock low pulse width 2.5 C ns 6 t t transition tim 0.3 1.2 ns setup and hold times 7 t is input setup time 1.5 C ns 5 8 t ih input hold time 0.8 C ns 5 9 t cks input setup time 1.5 C ns 5 10 t ckh cke hold time 0.8 C ns 5 11 t rsc mode register set-up time 15 C ns 12 t sb power down mode entry time 0 7.5 ns common parameters 13 t rcd row to column delay time 20 C ns 6 14 t rp row precharge time 20 C ns 6 15 t ras row active time 45 100k ns 6 16 t rc row cycle time 60 C ns 6 17 t rrd activate(a) to activate(b) command period 15 C ns 6 18 t ccd cas (a) to cas (b) command period 1 C clk refresh cycle 19 t ref refresh period (4096 cycles) 64 ms 20 t srex self refresh exit time 10 ns
8 v43648y04v(c)tg-75 re v . 1.3 october 2000 mosel vitelic v43648y04v(c)tg-75 notes: 1. the specified values are valid when addresses are changed no more than once during t ck (min.) and when no operation commands are registered on every rising clock edge during t rc (min). values are shown per module bank. 2. the specified values are valid when data inputs (dqs) are stable during t rc (min.). 3. all ac characteristics are shown for device level. an initial pause of 100 m s is required after power-up, then a precharge all banks command must be given followed by 8 auto refresh (cbr) cycles before the mode register set operation can begin. 4. ac timing tests have v il = 0.4v and v ih = 2.4v with the timing referenced to the 1.4v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1 ns with the ac output load circuit shown. specific tac and toh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1v / ns edge rate between 0.8v and 2.0v. read cycle 21 t oh data out hold time 2.7 C ns 2 22 t lz data out to low impedance time 1 C ns 23 t hz data out to high impedance time C 5.4 ns 7 24 t dqz dqm data out disable latency C 2 clk write cycle 25 t wr write recovery time 1 C clk 26 t dqw dqm write mask latency 0 C clk ac characteristics t a = 0 to 70 c; v ss = 0v; v cc = 3.3v 0.3v, t t = 1 ns (continued) # symbol parameter limit values unit note -75 min. max. 1.4v 1.4v tsetup thold tac tac tlz toh thz clock input output 50 pf i/o z=50 ohm + 1.4 v 50 ohm 2.4v 0.4v t t tcl tch i/o measurement conditions for tac and toh 50 pf
mosel vitelic v43648y04v(c)tg-75 9 v43648y04v(c)tg-75 re v . 1.3 october 2000 5. if clock rising time is longer than 1 ns, a time (t t /2 -0.5) ns has to be added to this parameter. 6. rated at 1.5v 7. if t t is longer than 1 ns, a time (t t -1) ns has to be added to this parameter. 8. any time that the refresh period has been exceeded, a minimum of two auto (cbr) refresh commands must be given to wake-up the device. 9. self refresh exit is a synchronous operation and begins on the 2nd positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to t rc is satisfied once the self refresh exit command is reg- istered. 10. referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 11. t dal is equivalent to t dpl + t rp . package diagram 144 pin sodimm v43648y04v(c)tg-75 -04 2.661 1.25 0.039 0.140 0.787 1 pin 2 on bac kside 3.3v pin 144 on bac kside 28 29 143 no te: 1. all dimensions in inches . t oler ances 0.005 unless otherwise specified.
10 v43648y04v(c)tg-75 re v . 1.3 october 2000 mosel vitelic v43648y04v(c)tg-75 label information c l = 3 (clk) t rcd = 3 (clk) t rp = 3 (clk) t ac = 5.4 ns v43648y04v(c)tg-75-05 333 u unbuffered dimm pc133 54 jedec spd revision 2.0 2 V43648Y04VCTG-75 pc133u-333-542-a taiwan xxxx-xxxxxxx a gerber file intel pc100 x 8 based - - - mosel vitelic part number dimm manufacture date code trace code criteria of pc100 or pc133 (refer to mvi datasheet)
mosel vitelic w orld wide offices v43648y04v(c)tg-75 ? cop yr ight 2000, mosel vitelic inc. 10/00 pr inted in u .s .a. mosel vitelic 3910 n. first street, san jose , ca 95134-1501 ph: (408) 433-6000 f ax: (408) 433-0952 tlx: 371-9461 the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. u .s. sales offices u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 hong kong 19 dai fu street taipo industrial estate taipo, nt, hong kong phone: 852-2666-3307 fax: 852-2770-8011 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 886-2-2545-1213 fax: 886-2-2545-1209 no 19 li hsin road science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-579-5888 fax: 886-3-566-5888 singapore 10 anson road #23-13 international plaza singapore 079903 phone: 65-3231801 fax: 65-3237013 japan wbg marive west 25f 6, nakase 2-chome mihama-ku, chiba-shi chiba 261-7125 phone: 81-43-299-6000 fax: 81-43-299-6555 uk & ireland suite 50, grovewood business centre strathclyde business park bellshill, lanarkshire, scotland, ml4 3nq phone: 01698-748515 fax: 01698-748516 germany (continental europe & israel) 71083 herrenberg benzstr. 32 germany phone: +49 7032 2796-0 fax: +49 7032 2796 22 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 southwestern 302 n. el camino real #200 san clemente, ca 92672 phone: 949-361-7873 fax: 949-361-7807 central, northeastern & southeastern 604 fieldwood circle richardson, tx 75081 phone: 972-690-1402 fax: 972-690-0341

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